Renesas Electronics recently announced the release of its first 32-bit CPU core based on the RISC-V open-standard instruction set architecture (ISA). This development represents Renesas’ entry into the RISC-V based market. The new CPU core will be compatible with Renesas’ e2 studio IDE, in addition to supporting third-party IDEs tailored for RISC-V based MCUs, facilitating […]
from LinuxGizmos.com https://ift.tt/y1caTiq
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